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mc56f844xx mc56f844xx advance information supports the 56f84462vlh, 56f84452vlh, 56f84451vlf, 56f84442vlh, 56F84441VLF features ? this family of digital signal controllers (dscs) is based on the 32-bit 56800ex core. each device combines, on a single chip, the processing power of a dsp and the functionality of an mcu with a flexible set of peripherals to support many target applications: C industrial control C home appliances C smart sensors C fire and security systems C switched-mode power supply and power management C uninterruptible power supply (ups) C solar and wind power generator C power metering C motor control (acim, bldc, pmsm, sr, stepper) C handheld power tools C circuit breaker C medical device/equipment C instrumentation C lighting ? dsc based on 32-bit 56800ex core C up to 60 mips at 60 mhz core frequency C dsp and mcu functionality in a unified, c-efficient architecture ? on-chip memory C up to 160 kb (128 kb + 32 kb) flash memory, including up to 32 kb flexnvm C up to 24 kb ram C up to 2 kb flexram with eee capability C 60 mhz program execution from both internal flash memory and ram C on-chip flash memory and ram can be mapped into both program and data memory spaces ? analog C two high-speed, 8-channel, 12-bit adcs with dynamic x2, x4 programmable amplifier C one 20-channel, 16-bit adc C up to four analog comparators with integrated 6-bit dac references C one 12-bit dac ? pwms and timers C one eflexpwm module with up to 24 pwm outputs C two 16-bit quad timer (2 x 4 16-bit timers) C two periodic interval timers (pits) C one quadrature decoder C two programmable delay blocks (pdbs) ? communication interfaces C two high-speed queued sci (qsci) modules with lin slave functionality C two queued spi (qspi) modules C two smbus-compatible i2c ports C one flexible controller area network (flexcan) module ? security and integrity C cyclic redundancy check (crc) generator C computer operating properly (cop) watchdog C external watchdog monitor (ewm) ? clocks C two on-chip relaxation oscillators: 8 mhz (400 khz at standby mode) and 32 khz C crystal / resonator oscillator ? system C dma controller C integrated power-on reset (por) and low-voltage interrupt (lvi) and brown-out reset module C inter-module crossbar connection C jtag/enhanced on-chip emulation (eonce) for unobtrusive, real-time debugging freescale semiconductor document number: mc56f844xx data sheet: advance information rev. 2, 06/2012 this document contains information on a new product. specifications and information herein are subject to change without notice. ? 2012 freescale semiconductor, inc. preliminary general business information
? operating characteristics C single supply: 3.0 v to 3.6 v C 5 vCtolerant i/o ? lqfp packages: C 48-pin C 64-pin mc56f844xx advance information data sheet, rev. 2, 06/2012. 2 preliminary freescale semiconductor, inc. general business information
table of contents 1 overview ................................................................................. 4 1.1 mc56f844x/5x/7x product family ................................ 4 1.2 56800ex 32-bit digital signal controller core .............. 5 1.3 operation parameters ................................................... 6 1.4 on-chip memory and memory protection ..................... 6 1.5 interrupt controller ........................................................ 7 1.6 peripheral highlights ...................................................... 7 1.7 block diagrams ............................................................. 13 2 signal groups .......................................................................... 16 3 ordering parts ......................................................................... 16 3.1 determining valid orderable parts ................................. 16 4 part identification..................................................................... 16 4.1 description .................................................................... 17 4.2 format ........................................................................... 17 4.3 fields ............................................................................. 17 4.4 example ........................................................................ 17 5 terminology and guidelines .................................................... 18 5.1 definition: operating requirement ................................. 18 5.2 definition: operating behavior ....................................... 18 5.3 definition: attribute ........................................................ 19 5.4 definition: rating ........................................................... 19 5.5 result of exceeding a rating .......................................... 19 5.6 relationship between ratings and operating requirements ................................................................. 20 5.7 guidelines for ratings and operating requirements ....... 20 5.8 definition: typical value ................................................ 21 5.9 typical value conditions ................................................ 22 6 ratings .................................................................................... 22 6.1 thermal handling ratings ............................................... 22 6.2 moisture handling ratings .............................................. 22 6.3 esd handling ratings..................................................... 22 6.4 voltage and current operating ratings ........................... 23 7 general ................................................................................... 24 7.1 general characteristics ................................................. 24 7.2 ac electrical characteristics ......................................... 25 7.3 nonswitching electrical specifications ........................... 26 7.4 switching specifications ................................................ 31 7.5 thermal specifications................................................... 32 8 peripheral operating requirements and behaviors .................. 34 8.1 core modules ................................................................ 34 8.2 system modules ............................................................ 35 8.3 clock modules ............................................................... 35 8.4 memories and memory interfaces ................................. 38 8.5 analog ........................................................................... 41 8.6 pwms and timers .......................................................... 51 8.7 communication interfaces ............................................. 52 9 design considerations ............................................................ 58 9.1 thermal design considerations .................................... 58 9.2 electrical design considerations................................... 60 10 obtaining package dimensions ............................................... 61 11 pinout ...................................................................................... 61 11.1 signal multiplexing and pin assignments...................... 61 11.2 pinout diagrams ............................................................ 63 12 product documentation........................................................... 65 13 revision history ...................................................................... 66 mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 3 general business information
overview 1.1 mc56f844x/5x/7x product family the following table highlights major features, including features that differ among members of the family. features not listed are shared by all members of the family. table 1. 56f844x/5x/7x family part number mc56f84 789 786 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441 core frequency (mhz) 100 100 100 100 100 80 80 80 80 80 80 80 80 60 60 60 60 60 flash memory (kb) 256 256 128 128 128 96 96 64 64 256 256 128 128 128 96 96 64 64 flevnvm/ flexram (kb) 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 32/2 total flash memory, including flexnvm (kb) 1 288 288 160 160 160 128 128 96 96 288 288 160 160 160 128 128 96 96 ram (kb) 32 32 24 24 24 16 16 8 8 32 32 24 24 24 16 16 8 8 memory resource protection yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes external watchdog 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12-bit cyclic adc channels 2x8 (300 ns) 2x8 (300 ns) 2x8 (300 ns) 2x8 (300 ns) 2x8 (300 ns) 2x8 (300 ns) 2x5 (300 ns) 2x8 (300 ns) 2x5 (300 ns) 2x8 (600 ns) 2x8 (600 ns) 2x8 (600 ns) 2x8 (600 ns) 2x8 (600 ns) 2x8 (600 ns) 2x5 (600 ns) 2x8 (600 ns) 2x5 (600 ns) 16-bit sar adc (with temp sensor) channels 1x 16 1x 10 1x 16 1x 10 1x8 1x8 0 1x8 0 1x 16 1x 10 1x 16 1x 10 0 1x8 0 1x8 0 pwma with input capture: high- resolution channels 1x8 1x8 1x8 1x8 1x8 1x8 1x6 1x8 1x6 0 0 0 0 0 0 0 0 0 table continues on the next page... 1 overview mc56f844xx advance information data sheet, rev. 2, 06/2012. 4 preliminary freescale semiconductor, inc. general business information
table 1. 56f844x/5x/7x family (continued) part number mc56f84 789 786 769 766 763 553 550 543 540 587 585 567 565 462 452 451 442 441 standard channels 4 1 4 1 1 1 0 1 0 2x 12 1x 12, 1x9 2x 12 1x 12, 1x9 1x9 1x9 1x6 1x9 1x6 pwmb with input capture: standard channels 1x 12 1x7 1x 12 1x7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dac 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 quad decoder 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 dma yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes cmp 4 4 4 4 4 4 3 4 3 4 4 4 4 4 4 3 4 3 qsci 3 3 3 3 2 2 2 2 2 3 3 3 3 2 2 2 2 2 qspi 3 2 3 2 2 2 2 2 2 3 2 3 2 2 2 2 2 2 i2c/smbus 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 flexcan 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 lqfp package pin count 100 80 100 80 64 64 48 64 48 100 80 100 80 64 64 48 64 48 1. this total assumes no flexnvm is used with flexram for eeprom. 1.2 56800ex 32-bit digital signal controller core ? efficient 32-bit 56800ex digital signal processor (dsp) engine with modified dual harvard architecture ? three internal address buses ? four internal data buses: two 32-bit primary buses, one 16-bit secondary data bus, and one 16-bit instruction bus ? 32-bit data accesses ? support for concurrent instruction fetches in the same cycle and dual data accesses in the same cycle ? 20 addressing modes ? as many as 60 million instructions per second (mips) at 60 mhz core frequency ? 162 basic instructions ? instruction set supports both fractional arithmetic and integer arithmetic ? 32-bit internal primary data buses supporting 8-bit, 16-bit, and 32-bit data movement, addition, subtraction, and logical operation ? single-cycle 16 16-bit -> 32-bit and 32 x 32-bit -> 64-bit multiplier-accumulator (mac) with dual parallel moves overview mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 5 general business information
? 32-bit arithmetic and logic multi-bit shifter ? four 36-bit accumulators, including extension bits ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? bit reverse address mode, effectively supporting dsp and fast fourier transform algorithms ? full shadowing of the register stack for zero-overhead context saves and restores: nine shadow registers corresponding to the r0, r1, r2, r3, r4, r5, n, n3, and m01 address registers ? instruction set supporting both dsp and controller functions ? controller-style addressing modes and instructions for compact code ? enhanced bit manipulation instruction set ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? priority level setting for interrupt levels ? jtag/enhanced on-chip emulation (once) for unobtrusive, real-time debugging that is independent of processor speed 1.3 operation parameters ? up to 60 mhz operation at -40 c to 105 c ambient temperature ? single 3.3 v power supply ? supply range: v dd - v ss = 2.7 v to 3.6 v, v dda - v ssa = 2.7 v to 3.6 v 1.4 on-chip memory and memory protection ? modified dual harvard architecture permits as many as three simultaneous accesses to program and data memory ? internal flash memory with security and protection to prevent unauthorized access ? memory resource protection (mrp) unit to protect supervisor programs and resources from user programs ? programming code can reside in flash memory during flash programming ? the dual-ported ram controller supports concurrent instruction fetches and data accesses, or dual data accesses, by the dsc core. ? concurrent accesses provide increased performance. ? the data and instruction arrive at the core in the same cycle, reducing latency. ? on-chip memory ? up to 128 kw program/data flash memory ? up to 16 kw dual port data/program ram overview mc56f844xx advance information data sheet, rev. 2, 06/2012. 6 preliminary freescale semiconductor, inc. general business information
? up to 16 kw flexnvm, which can be used as additional program or data flash memory ? up to 1 kw flexram, which can be configured as enhanced eeprom (used in conjunction with flexnvm) or used as additional ram 1.5 interrupt controller ? five interrupt priority levels ? three user programmable priority levels for each interrupt source: level 0, 1, 2 ? unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, swi3 instruction ? maskable level 3 interrupts include: eonce step counter, eonce breakpoint unit, eonce trace buffer ? lowest-priority software interrupt: level lp ? support for nested interrupt: higher priority level interrupt request can interrupt lower priority interrupt subroutine ? masking of interrupt priority level managed by the 56800ex core ? two programmable fast interrupts that can be assigned to any interrupt source ? notification to system integration module (sim) to restart clock when in wait and stop states ? ability to relocate interrupt vector table peripheral highlights 1.6.1 enhanced flex pulse width modulator (eflexpwm) ? up to 12 output channels in each module ? 16 bits of resolution for center, edge aligned, and asymmetrical pwms ? pwma with accumulative fractional clock calculation ? accumulative fractional clock calculation improves the resolution of the pwm period and edge placement ? arbitrary pwm edge placement ? equivalent to 312 ps pwm frequency and duty-cycle resolution on average ? each complementary pair can operate with its own pwm frequency base and deadtime values ? 4 time base in each pwm module ? independent top and bottom deadtime insertion for each complementary pair ? pwm outputs can operate as complementary pairs or independent channels ? independent control of both edges of each pwm output 1.6 peripheral highlights mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 7 general business information
? enhanced input capture and output compare functionality on each input ? channels not used for pwm generation can be used for buffered output compare functions ? channels not used for pwm generation can be used for input capture functions ? enhanced dual edge capture functionality ? synchronization to external hardware or other pwm supported ? double buffered pwm registers ? integral reload rates from 1 to 16 ? half-cycle reload capability ? multiple output trigger events can be generated per pwm cycle via hardware ? support for double switching pwm outputs ? up to eight fault inputs can be assigned to control multiple pwm outputs ? programmable filters for fault inputs ? independently programmable pwm output polarity ? individual software control of each pwm output ? all outputs can be programmed to change simultaneously via a force_out event ? pwmx pin can optionally output a third pwm signal from each submodule ? option to supply the source for each complementary pwm signal pair from any of the following: ? crossbar module outputs ? external adc input, taking into account values set in adc high and low limit registers 1.6.2 12-bit analog-to-digital converter (cyclic type) ? two independent 12-bit analog-to-digital converters (adcs) ? 2 x 8-channel external inputs ? built-in x1, x2, x4 programmable gain pre-amplifier ? maximum adc clock frequency is up to 20 mhz with 50 ns period ? single conversion time of 8.5 adc clock cycles ? additional conversion time of 6 adc clock cycles ? sequential, parallel, and independent scan mode ? first 8 samples have offset, limit and zero-crossing calculation supported ? adc conversions can be synchronized by any module connected to internal crossbar module, such as pwm and timer modules and gpio and comparators ? support for simultaneous and software triggering conversions ? support for multi-triggering mode with a programmable number of conversions on each trigger ? each adc has ability to scan and store up to 8 conversion results peripheral highlights mc56f844xx advance information data sheet, rev. 2, 06/2012. 8 preliminary freescale semiconductor, inc. general business information
1.6.3 inter-module crossbar and and-or-invert logic ? provides generalized connections between and among on-chip peripherals: adcs, 12-bit dac, comparators, quad timers, eflexpwms, pdbs, ewm, quadrature decoder, and select i/o pins ? user-defined input/output pins for all modules connected to crossbar ? dma request and interrupt generation from crossbar ? write-once protection for all registers ? and-or-invert function that provides a universal boolean function generator using a four-term sum-of-products expression, with each product term containing true or complement values of the four selected inputs (a, b, c, d). 1.6.4 comparator ? full rail-to-rail comparison range ? support for high speed mode and low speed mode ? selectable input source includes external pins and internal dacs ? programmable output polarity ? 6-bit programmable dac as voltage reference per comparator ? three programmable hysteresis levels ? selectable interrupt on rising edge, falling edge, or toggle of comparator output 1.6.5 12-bit digital-to-analog converter ? 12-bit resolution ? powerdown mode ? automatic mode allows the dac to automatically generate pre-programmed output waveforms including square, triangle, and sawtooth waveforms for applications such as slope compensation ? programmable period, update rate, and range ? output can be routed to an internal comparator, adc, or optionally off chip 1.6.6 quad timer ? four 16-bit up/down counters with programmable prescaler for each counter ? operation modes: edge count, gated count, signed count, capture, compare, pwm, signal shot, single pulse, pulse string, cascaded, quadrature decode ? programmable input filter ? counting start can be synchronized across counters peripheral highlights mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 9 general business information
1.6.7 queued serial communications interface (qsci) modules ? operating clock up to two times cpu operating frequency ? four-word-deep fifos available on both transmit and receive buffers ? standard mark/space non-return-to-zero (nrz) format ? 13-bit integer and 3-bit fractional baud rate selection ? full-duplex or single-wire operation ? programmable 8-bit or 9-bit data format ? error detection capability ? two receiver wakeup methods: ? idle line ? address mark ? 1/16 bit-time noise detection 1.6.8 queued serial peripheral interface (qspi) modules ? maximum 25 mbps baud rate ? selectable baud rate clock sources for low baud rate communication ? baud rate as low as baudrate_freq_in / 8192 ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? four-word-deep fifos available on transmit and receive buffers ? programmable length transmissions (2 bits to 16 bits) ? programmable transmit and receive shift order (msb as first bit transmitted) 1.6.9 inter-integrated circuit (i2c)/system management bus (smbus) modules ? compatible with i2c bus standard ? support for system management bus (smbus) specification, version2 ? multi-master operation ? general call recognition ? 10-bit address extension ? dual slave addresses ? programmable glitch input filter 1.6.10 flex controller area network (flexcan) module ? clock source from pll or xosc/clkin peripheral highlights mc56f844xx advance information data sheet, rev. 2, 06/2012. 10 preliminary freescale semiconductor, inc. general business information
? implementation of the can protocol version 2.0 a/b ? standard and extended data frames ? 0-to-8 bytes data length ? programmable bit rate up to 1 mbps ? support for remote frames ? sixteen message buffers, each configurable as receive or transmit, all supporting standard and extended messages ? individual rx mask registers per message buffer ? internal timer for time-stamping of received and transmitted messages ? listen-only mode capability ? programmable loopback mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number, or highest priority ? global network time, synchronized by a specific message ? low power modes, with programmable wakeup on bus activity 1.6.11 computer operating properly (cop) watchdog ? programmable timeout period ? support for operation in all power modes: run mode, wait mode, stop mode ? causes loss of reference reset 128 cycles after loss of reference clock to the pll is detected ? selectable reference clock source in support of en60730 and iec61508 ? selectable clock sources: ? external crystal oscillator/external clock source ? on-chip low-power 32 khz oscillator ? system bus (ipbus up to 60 mhz) ? 8 mhz / 400 khz rosc ? support for interrupt triggered when the counter reaches the timeout value 1.6.12 power supervisor ? power-on reset (por) to reset cpu, peripherals, and jtag/eonce controllers (vdd > 2.1 v) ? brownout reset (vdd < 1.9 v) ? critical warn low voltage interrupt (lvi2.0) ? peripheral low voltage interrupt (lvi2.7) peripheral highlights mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 11 general business information
1.6.13 phase locked loop ? wide programmable output frequency: 240 mhz to 400 mhz ? input reference clock frequency: 8 mhz to 16 mhz ? detection of loss of lock and loss of reference clock ? ability to power down clock sources 1.6.14.1 on-chip oscillators ? tunable 8 mhz relaxation oscillator with 400 khz at standby mode (divide-by-two output) ? 32 khz low frequency clock as secondary clock source for cop, ewm, pit 1.6.14.2 crystal oscillator ? support for both high esr crystal oscillator (greater than 100-ohm esr) and ceramic resonator ? 4 mhz to 16 mhz operating frequency 1.6.15 cyclic redundancy check (crc) generator ? hardware 16/32-bit crc generator ? high-speed hardware crc calculation ? programmable initial seed value ? programmable 16/32-bit polynomial ? error detection for all single, double, odd, and most multi-bit errors ? option to transpose input data or output data (crc result) bitwise or bytewise, 1 which is required for certain crc standards ? option for inversion of final crc result 1.6.16 general purpose i/o (gpio) ? 5 v tolerance ? individual control of peripheral mode or gpio mode for each pin ? programmable push-pull or open drain output ? configurable pullup or pulldown on all input pins 1.6.14 1. a bytewise transposition is not possible when accessing the crc data register via 8-bit accesses. in this case, user software must perform the bytewise transposition. clock sources mc56f844xx advance information data sheet, rev. 2, 06/2012. 12 preliminary freescale semiconductor, inc. general business information
? all pins except jtag and resetb pins default to be gpio inputs ? 2 ma / 9 ma source/sink capability ? controllable output slew rate 1.7 block diagrams the 56800ex core is based on a modified dual harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the mcu-style programming model and optimized instruction set allow straightforward generation of efficient, compact dsp and control code. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. the device's basic architecture appears in figure 1 and figure 2 . figure 1 illustrates how the 56800ex system buses communicate with internal memories and the ipbus interface and the internal connections among each unit of the 56800ex core. figure 2 shows the peripherals and control blocks connected to the ipbus bridge. see the specific devices reference manual for details. clock sources mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 13 general business information
data arithmetic logic unit (alu) xab2 pab pdb cdbw cdbr xdb2 program memory data/ ipbus interface bit- manipulation unit m01 address xab1 generation unit (agu) pc la la2 hws0 hws1 fira omr sr fisr lc lc2 instruction decoder interrupt unit looping unit program control unit alu1 alu2 mac and alu a1a2 a0 b1b2 b0 c1c2 c0 d1d2 d0 y1 y0 x0 enhanced jtag tap r2 r3 r4 r5 sp r0 r1 y multi-bit shifter once? program ram dsp56800ex core n3 r2 r3 r4 r5 n figure 1. 56800ex basic block diagram clock sources mc56f844xx advance information data sheet, rev. 2, 06/2012. 14 preliminary freescale semiconductor, inc. general business information
memory resource protection unit eonce 56800ex cpu program bus core data bus secondary data bus flash controller and cache program/data flash up to 128kb data flash 32kb flexram 2kb data/program ram up to 24kb dma controller interrupt controller flexcan qsci 0,1 qspi 0,1 i2c 0,1 quad timer a & b periodic interrupt timer (pit) 0, 1 eflexpwm a pdb 0, 1 adc a 12bit adc b 12bit adc c 16bit comparators with 6bit dac a,b,c,d watchdog (cop) ewm quadrature decoder crc dac 12bit inter-module crossbar b inter-module crossbar a and-or-inv logic inter module connection gpio & peripheral mux platform bus crossbar swirch crystal osc internal 8 mhz internal 32 khz pll power management controller (pmc) system integration module (sim) package pins peripheral bus peripheral bus peripheral bus 4 jtag inter module crossbar inputs inter module crossbar outputs clock mux program controller (pc) address generation unit (agu) arithmetic logic unit (alu) bit manipulation unit inter module crossbar outputs inter module crossbar inputs figure 2. system diagram clock sources mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 15 general business information
2 signal groups the input and output signals of the mc56f84xxx are organized into functional groups, as detailed in table 2 . table 2. functional group pin allocations functional group number of pins in 48lqfp number of pins in 64lqfp number of pins in 80lqfp number of pins in 100lqfp power inputs (v dd , v dda , v cap ) 5 6 6 6 ground (v ss , v ssa ) 4 4 4 4 reset 1 1 1 1 eflexpwm ports, not including fault pins 6 9 n/a n/a queued serial peripheral interface (qspi) ports 5 6 8 15 queued serial communications interface (qsci) ports 6 9 13 15 inter-integrated circuit (i 2 c) interface ports 4 6 6 6 12-bit analog-to-digital converter (cyclic adc) inputs 10 16 16 16 16-bit analog-to-digital converter (sar adc) inputs 2 8 10 16 analog comparator inputs/outputs 10/4 13/6 13/6 16/6 12-bit digital-to-analog output 1 1 1 1 quad timer module (tmr) ports 6 9 11 13 controller area network (flexcan) 2 2 2 2 inter-module crossbar inputs/outputs 12/2 16/6 19/17 25/19 clock inputs/outputs 2/2 2/2 2/3 2/3 jtag / enhanced on-chip emulation (eonce) 4 4 4 4 3 ordering parts 3.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to www.freescale.com and perform a part number search for the following device numbers: mc56f84 4 part identification signal groups mc56f844xx advance information data sheet, rev. 2, 06/2012. 16 preliminary freescale semiconductor, inc. general business information
4.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 4.2 format part numbers for this device have the following format: q 56f8 4 c f p t pp n 4.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? mc = fully qualified, general market flow ? pc = prequalification 56f8 dsc family with flash memory and dsp56800/ dsp56800e/dsp56800ex core ? 56f8 4 dsc subfamily ? 4 c maximum cpu frequency (mhz) ? 4 = 60 mhz ? 5 = 80 mhz ? 7 = 100 mhz f primary program flash memory size ? 4 = 64 kb ? 5 = 96 kb ? 6 = 128 kb ? 8 = 256 kb p pin count ? 0 and 1 = 48 ? 2 and 3 = 64 ? 4, 5, and 6 = 80 ? 7, 8, and 9 = 100 t temperature range (c) ? v = C40 to 105 pp package identifier ? lf = 48lqfp ? lh = 64lqfp ? lk = 80lqfp ? ll = 100lqfp n packaging type ? r = tape and reel ? (blank) = trays part identification mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 17 general business information
4.4 example this is an example part number: mc56f84789vll 5 terminology and guidelines 5.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 5.1.1 example this is an example of an operating requirement, which you must meet for the accompanying operating behaviors to be guaranteed: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 5.2 definition: operating behavior an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 5.2.1 example this is an example of an operating behavior, which is guaranteed if you meet the accompanying operating requirements: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a terminology and guidelines mc56f844xx advance information data sheet, rev. 2, 06/2012. 18 preliminary freescale semiconductor, inc. general business information
5.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 5.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 5.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 5.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v terminology and guidelines mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 19 general business information
5.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 5.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 5.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. terminology and guidelines mc56f844xx advance information data sheet, rev. 2, 06/2012. 20 preliminary freescale semiconductor, inc. general business information
5.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 5.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 5.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j terminology and guidelines mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 21 general business information
5.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 6 ratings 6.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 6.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . ratings mc56f844xx advance information data sheet, rev. 2, 06/2012. 22 preliminary freescale semiconductor, inc. general business information
6.3 esd handling ratings although damage from electrostatic discharge (esd) is much less common on these devices than on early cmos circuits, use normal handling precautions to avoid exposure to static discharge. qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qualification. during the device qualification esd stresses were performed for the human body model (hbm), the machine model (mm), and the charge device model (cdm). all latch-up testing is in conformity with aec-q100 stress test qualification. a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. table 3. esd/latch-up protection characteristic 1 min max unit esd for human body model (hbm) C2000 +2000 v esd for machine model (mm) C200 +200 v esd for charge device model (cdm) C500 +500 v latch-up current at ta= 85c (i lat ) C100 +100 ma 1. parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. 6.4 voltage and current operating ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 4 may affect device reliability or cause permanent damage to the device. table 4. absolute maximum ratings (v ss = 0 v, v ssa = 0 v) characteristic symbol notes 1 min max unit supply voltage range v dd -0.3 4.0 v analog supply voltage range v dda -0.3 4.0 v adc high voltage reference v refhx -0.3 4.0 v voltage difference v dd to v dda v dd -0.3 0.3 v voltage difference v ss to v ssa v ss -0.3 0.3 v table continues on the next page... ratings mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 23 general business information
table 4. absolute maximum ratings (v ss = 0 v, v ssa = 0 v) (continued) characteristic symbol notes 1 min max unit digital input voltage range v in pin groups 1, 2 -0.3 5.5 v oscillator input voltage range v osc pin group 4 -0.4 4.0 v analog input voltage range v ina pin group 3 -0.3 4.0 v input clamp current, per pin (v in < v ss - 0.3 v) 2 , 3 v ic -5.0 ma output clamp current, per pin 4 v oc 20.0 ma contiguous pin dc injection currentregional limit sum of 16 contiguous pins i icont -25 25 ma output voltage range (normal push-pull mode) v out pin group 1 -0.3 4.0 v output voltage range (open drain mode) v outod pin group 2 -0.3 5.5 v dac output voltage range v out_dac pin group 5 -0.3 4.0 v ambient temperature industrial t a -40 105 c storage temperature range (extended industrial) t stg -55 150 c 1. default mode ? pin group 1: gpio, tdi, tdo, tms, tck ? pin group 2: reset, gpioa7 ? pin group 3: adc and comparator analog inputs ? pin group 4: xtal, extal ? pin group 5: dac analog output 2. continuous clamp current 3. all 5 volt tolerant digital i/o pins are internally clamped to vss through a esd protection diode. there is no diode connection to vdd. if vin greater than vdio_min (=vss-0.3v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. 4. i/o is configured as push-pull mode. 7 general 7.1 general characteristics the device is fabricated in high-density, low-power cmos with 5 vCtolerant ttl- compatible digital inputs. the term 5 vCtolerant refers to the capability of an i/o pin, built on a 3.3 vCcompatible process technology, to withstand a voltage up to 5.5 v without damaging the device. 5 vCtolerant i/o is desirable because many systems have a mixture of devices designed for 3.3 v and 5 v power supplies. in such systems, a bus may carry both 3.3 vC and 5 vC compatible i/o voltage levels (a standard 3.3 v i/o is designed to receive a maximum voltage of 3.3 v 10% during normal operation without causing damage). this 5 vC tolerant capability therefore offers the power savings of 3.3 v i/o levels combined with the ability to receive 5 v levels without damage. general mc56f844xx advance information data sheet, rev. 2, 06/2012. 24 preliminary freescale semiconductor, inc. general business information
absolute maximum ratings in table 4 are stress ratings only, and functional operation at the maximum is not guaranteed. stress beyond these ratings may affect device reliability or cause permanent damage to the device. unless otherwise stated, all specifications within this chapter apply over the temperature range of -40c to 105c ambient temperature over the following supply ranges: vss = vssa = 0 v, vdd = vdda = 3.0 v to 3.6 v, cl 50 pf, f op = 60 mhz. caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, normal precautions are advised to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. 7.2 ac electrical characteristics tests are conducted using the input levels specified in table 7 . unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured between the 10% and 90% points, as shown in figure 3 . ? v ih v il fall time midpoint1 low high 90% 50% 10% rise time the midpoint is v il + (v ih C v il )/2. input signal figure 3. input signal measurement references figure 4 shows the definitions of the following signal states: ? active state, when a bus or signal is driven, and enters a low impedance state ? tri-stated, when a bus or signal is placed in a high impedance state ? data valid state, when a signal level has reached v ol or v oh ? data invalid state, when a signal level is in transition between v ol and v oh general mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 25 general business information
? data invalid state data1 data3 valid data2 data3 data1 valid data active data active data2 valid data three-stated figure 4. signal states 7.3 nonswitching electrical specifications 7.3.1 voltage and current operating requirements this section includes information about recommended operating conditions. note recommended v dd ramp rate is between 1 ms and 200 ms. table 5. recommended operating conditions (v reflx = 0 v, v ssa = 0 v, v ss = 0 v) characteristic symbol notes 1 min typ max unit supply voltage 2 v dd , v dda 2.7 3.3 3.6 v adc (cyclic) reference voltage high v refha v refhb 3.0 v dda v adc (sar) reference voltage high v refhc 2.0 v dda v voltage difference v dd to v dda vdd -0.1 0 0.1 v voltage difference v ss to v ssa vss -0.1 0 0.1 v input voltage high (digital inputs) v ih pin groups 1, 2 0.7 x v dd 5.5 v input voltage low (digital inputs) v il pin groups 1, 2 0.35 x v dd v oscillator input voltage high xtal driven by an external clock source v ihosc pin group 4 2.0 v dd + 0.3 v oscillator input voltage low v ilosc pin group 4 -0.3 0.8 v output source current high (at v oh min.) 3 ? programmed for low drive strength ? programmed for high drive strength i oh pin group 1 pin group 1 -2 -9 ma output source current low (at v ol max.) 3 ? programmed for low drive strength ? programmed for high drive strength i ol pin groups 1, 2 pin groups 1, 2 2 9 ma 1. default mode ? pin group 1: gpio, tdi, tdo, tms, tck ? pin group 2: reset, gpioa7 ? pin group 3: adc and comparator analog inputs general mc56f844xx advance information data sheet, rev. 2, 06/2012. 26 preliminary freescale semiconductor, inc. general business information
? pin group 4: xtal, extal ? pin group 5: dac analog output 2. adc (cyclic) specifications are not guaranteed when v dda is below 3.0 v. 3. total chip source or sink current cannot exceed 75 ma. 7.3.2 lvd and por operating requirements table 6. pmc low-voltage detection (lvd) and power-on reset (por) parameters characteristic symbol min typ max unit por assert voltage 1 por 2.0 v por release voltage 2 por 2.7 v lvi_2p7 threshold voltage 2.73 v lvi_2p2 threshold voltage 2.23 v 1. during 3.3-volt v dd power supply ramp down 2. during 3.3-volt v dd power supply ramp up (gated by lvi_2p7) 7.3.3 voltage and current operating behaviors the following table provides information about power supply requirements and i/o pin characteristics. table 7. dc electrical characteristics at recommended operating conditions characteristic symbol notes 1 min typ max unit test conditions output voltage high v oh pin group 1 v dd - 0.5 v i oh = i ohmax output voltage low v ol pin groups 1, 2 0.5 v i ol = i olmax digital input current high pull-up enabled or disabled i ih pin groups 1, 2 0 +/- 2.5 a v in = 2.4v to 5.5v comparator input current high i ihc pin group 3 0 +/- 2 a v in = v dda oscillator input current high i ihosc pin group 3 0 +/- 2 a v in = v dda internal pull-up resistance r pull-up 20 50 k? internal pull-down resistance r pull-down 20 50 k? comparator input current low i ilc pin group 3 0 +/- 2 a v in = 0v table continues on the next page... general mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 27 general business information
table 7. dc electrical characteristics at recommended operating conditions (continued) characteristic symbol notes 1 min typ max unit test conditions oscillator input current low i ilosc pin group 3 0 +/- 2 a v in = 0v dac output voltage range v dac pin group 5 typically v ssa + 40mv typically v dda - 40mv v r ld = 3 k? || c ld = 400 pf output current 1 high impedance state i oz pin groups 1, 2 0 +/- 1 a schmitt trigger input hysteresis v hys pin groups 1, 2 0.06 x v dd v 1. default mode ? pin group 1: gpio, tdi, tdo, tms, tck ? pin group 2: reset, gpioa7 ? pin group 3: adc and comparator analog inputs ? pin group 4: xtal, extal ? pin group 5: dac 7.3.4 power mode transition operating behaviors parameters listed are guaranteed by design. note all address and data buses described here are internal. table 8. reset, stop, wait, and interrupt timing characteristic symbol typical min typical max unit see figure minimum reset assertion duration t ra 16 1 ns reset deassertion to first address fetch t rda tbd 16 2 ns delay from interrupt assertion to fetch of first instruction (exiting stop) t if 361.3 570.9 ns 1. if reset pin filter is enabled, minimum pulse assertion must be greater than 21 ns 2. this value is true if the user sets to 1 the rst_flt bit in the sim_ctrl register. note in the formulae, t = system clock cycle and t osc = oscillator clock cycle. for an operating frequency of 60 mhz, t = 16.6 ns. at 4 mhz (used coming out of reset and stop modes), t = 250 ns. general mc56f844xx advance information data sheet, rev. 2, 06/2012. 28 preliminary freescale semiconductor, inc. general business information
7.3.5 power consumption operating behaviors table 9. current consumption mode maximum frequency conditions typical at 3.3 v, 25c maximum at 3.6 v, 105c i dd 1 i dda i dd 1 i dda run 60 mhz ? 60 mhz device clock ? regulators are in full regulation ? relaxation oscillator on ? pll powered on ? continuous mac instructions with fetches from program flash ? all peripheral modules enabled. ? tmrs and scis using 1x clock ? nanoedge within pwma using 2x clock ? adc/dac powered on and clocked at 5 mhz 2 ? comparator powered on tbd tbd tbd tbd wait 60 mhz ? 60 mhz device clock ? regulators are in full regulation ? relaxation oscillator on ? pll powered on ? processor core in wait state ? all peripheral modules enabled. ? tmrs and scis using 1x clock ? nanoedge within pwma using 2x clock ? adc/dac/comparator powered off tbd tbd tbd tbd stop 4 mhz ? 4 mhz device clock ? regulators are in full regulation ? relaxation oscillator on ? pll powered off ? processor core in stop state ? all peripheral module and core clocks are off ? adc/dac/comparator powered off tbd tbd tbd tbd lprun (lsrun) 2 mhz ? 200 khz device clock from relaxation oscillator (rosc) ? rosc in standby mode ? regulators are in standby ? pll disabled ? repeat nop instructions ? all peripheral modules enabled, except nanoedge and cyclic adcs 3 ? simple loop with running from platform instruction buffer tbd tbd tbd tbd lpwait (lswait) 2 mhz ? 200 khz device clock from relaxation oscillator (rosc) ? rosc in standby mode ? regulators are in standby ? pll disabled ? all peripheral modules enabled, except nanoedge and cyclic adcs 3 ? processor core in wait mode tbd tbd tbd tbd table continues on the next page... general mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 29 general business information
table 9. current consumption (continued) mode maximum frequency conditions typical at 3.3 v, 25c maximum at 3.6 v, 105c i dd 1 i dda i dd 1 i dda lpstop (lsstop) 2 mhz ? 200 khz device clock from relaxation oscillator (rosc) ? rosc in standby mode ? regulators are in standby ? pll disabled ? only pits and cop enabled; other peripheral modules disabled and clocks gated off 3 ? processor core in stop mode tbd tbd tbd tbd vlprun 200 khz ? 32 khz device clock ? clocked by a 32 khz external clock source ? oscillator in power down ? all roscs disabled ? large regulator is in standby ? small regulator is disabled ? pll disabled ? repeat nop instructions ? all peripheral modules, except cop and ewm, disabled and clocks gated off ? simple loop running from platform instruction buffer tbd tbd tbd tbd vlpwait 200 khz ? 32 khz device clock ? clocked by a 32 khz external clock source ? oscillator in power down ? all roscs disabled ? large regulator is in standby ? small regulator is disabled ? pll disabled ? all peripheral modules, except cop, disabled and clocks gated off ? processor core in wait mode tbd tbd tbd tbd vlpstop 200 khz ? 32 khz device clock ? clocked by a 32 khz external clock source ? oscillator in power down ? all roscs disabled ? large regulator is in standby ? small regulator is disabled ? pll disabled ? all peripheral modules, except cop, disabled and clocks gated off ? processor core in stop mode tbd tbd tbd tbd 1. no output switching, all ports configured as inputs, all inputs low, no dc loads 2. adc power consumption at higher frequency can be found in table 26 3. in all chip lp modes and flash memory vlp modes, the maximum frequency for flash memory operation is 500 khz due to the fixed frequency ratio of 1:4 between the cpu clock and the flash clock. general mc56f844xx advance information data sheet, rev. 2, 06/2012. 30 preliminary freescale semiconductor, inc. general business information
7.3.6 emc radiated emissions operating behaviors table 10. emc radiated emissions operating behaviors for symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 dbv v re3 radiated emissions voltage, band 3 150C500 dbv v re4 radiated emissions voltage, band 4 500C1000 dbv v re_iec iec level 0.15C1000 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 12 mhz (crystal), f sys = mhz, f bus = mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 7.3.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.freescale.com . 2. perform a keyword search for emc design. 7.3.8 capacitance attributes table 11. capacitance attributes description symbol min. typ. max. unit input capacitance c in 10 pf output capacitance c out 10 pf 7.4 switching specifications general mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 31 general business information
7.4.1 device clock specifications table 12. device clock specifications symbol description min. max. unit notes normal run mode f sysclk device (system and core) clock frequency ? using relaxation oscillator ? using external clock source 0.001 0 60 60 mhz f ipbus ip bus clock 60 mhz 7.4.2 general switching timing table 13. switching timing symbol description min max unit notes gpio pin interrupt pulse width 1 synchronous path 1.5 ip bus clock cycles 2 port rise and fall time (high drive strength), slew disabled 2.7 v dd 3.6v. 5.5 15.1 ns 3 port rise and fall time (high drive strength), slew enabled 2.7 v dd 3.6v. 1.5 6.8 ns 3 port rise and fall time (low drive strength). slew disabled . 2.7 v dd 3.6v 8.2 17.8 ns 4 port rise and fall time (low drive strength). slew enabled . 2.7 v dd 3.6v 3.2 9.2 ns 4 1. applies to a pin only when it is configured as gpio and configured to cause an interrupt by appropriately programming gpion_ipolr and gpion_ienr. 2. the greater synchronous and asynchronous timing must be met. 3. 75 pf load 4. 15 pf load 7.5 thermal specifications 7.5.1 thermal operating requirements table 14. thermal operating requirements symbol description min. max. unit t j die junction temperature C40 125 c t a ambient temperature (extended industrial) C40 105 c general mc56f844xx advance information data sheet, rev. 2, 06/2012. 32 preliminary freescale semiconductor, inc. general business information
7.5.2 thermal attributes this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user- determined rather than being controlled by the mcu design. to account for p i/o in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd is very small. see thermal design considerations for more detail on thermal design considerations. board type symbol description 48 lqfp 64 lqfp unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 70 64 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 46 46 c/w 1 , 3 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 57 52 c/w 1 , 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./ min. air speed) 39 39 c/w 1 , 3 r jb thermal resistance, junction to board 23 28 c/w 4 r jc thermal resistance, junction to case 17 15 c/w 5 jt thermal characterization parameter, junction to package top outside center (natural convection) 3 3 c/w 6 general mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 33 general business information
1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. for the lqfp, the board meets the jesd51-3 specification. 3. determined according to jedec standard jesd51-6, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horizontal. 4. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . board temperature is measured on the top surface of the board near the package. 5. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 6. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . peripheral operating requirements and behaviors 8.1 core modules 8.1.1 jtag timing table 15. jtag timing characteristic symbol min max unit see figure tck frequency of operation f op dc sys_clk/8 mhz figure 5 tck clock pulse width t pw 50 ns figure 5 tms, tdi data set-up time t ds 5 ns figure 6 tms, tdi data hold time t dh 5 ns figure 6 tck low to tdo data valid t dv 30 ns figure 6 tck low to tdo tri-state t ts 30 ns figure 6 tck (input) v m v il v m = v il + (v ih C v il )/2 t pw 1/f op t pw v m v ih figure 5. test clock input timing diagram 8 peripheral operating requirements and behaviors mc56f844xx advance information data sheet, rev. 2, 06/2012. 34 preliminary freescale semiconductor, inc. general business information
input data valid output data valid t ds t dh t dv t ts tck (input) tdi (input) tdo (output) tdo (output) tms figure 6. test access port timing diagram system modules 8.2.1 voltage regulator specifications the regulator supplies approximately 1.2 v to the mc56f84xxxs core logic. this regulator requires an external 2.2 f capacitor on each v cap pin for proper operation. ceramic and tantalum capacitors tend to provide better performance tolerances. the output voltage can be measured directly on the v cap pin. the specifications for this regulator are shown in table 16 . table 16. regulator 1.2 v parameters characteristic symbol min typ max unit output voltage 1 v cap 1.22 v short circuit current 2 i ss 600 tbd ma short circuit tolerance (v cap shorted to ground) t rsc 30 minutes 1. value is after trim 2. guaranteed by design table 17. bandgap electrical specifications characteristic symbol min typ max unit reference voltage (after trim) v ref 1.21 v 8.3 clock modules 8.2 system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 35 general business information
8.3.1 external clock operation timing parameters listed are guaranteed by design. table 18. external clock operation timing requirements characteristic symbol min typ max unit frequency of operation (external clock driver) 1 f osc 50 mhz clock pulse width 2 t pw 8 ns external clock input rise time 3 t rise 1 ns external clock input fall time 4 t fall 1 ns input high voltage overdrive by an external clock v ih 0.85vdd v input low voltage overdrive by an external clock v il 0.3v dd v 1. see figure 7 for detail on using the recommended connection of an external clock driver. 2. the chip may not function if the high or low pulse width is smaller than 6.25 ns. 3. external clock input rise time is measured from 10% to 90%. 4. external clock input fall time is measured from 90% to 10%. 90% 50% 10% 90% 50% 10% external clock t pw t pw t fall t rise v il v ih note: the midpoint is v il + (v ih C v il )/2. figure 7. external clock timing 8.3.2 phase locked loop timing table 19. phase locked loop timing characteristic symbol min typ max unit pll input reference frequency 1 f ref 8 8 16 mhz pll output frequency 2 f op 240 400 mhz pll lock time 3 t plls 35.5 73.2 s allowed duty cycle of input reference t dc 40 50 60 % 1. an externally supplied reference clock should be as free as possible from any phase jitter for the pll to work correctly. the pll is optimized for 8 mhz input. 2. the frequency of the core system clock cannot exceed 60 mhz. 3. this is the time required after the pll is enabled to ensure reliable operation. system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 36 preliminary freescale semiconductor, inc. general business information
8.3.3 external crystal or resonator requirement table 20. crystal or resonator requirement characteristic symbol min typ max unit frequency of operation f xosc 4 8 16 mhz 8.3.4 relaxation oscillator timing table 21. relaxation oscillator electrical specifications characteristic symbol min typ max unit 8 mhz output frequency 1 run mode ? 0c to 105c ? -40c to 105c standby mode (irc trimmed @ 8 mhz) ? -40c to 105c 7.84 7.76 tbd 8 8 tbd 8.16 8.24 tbd mhz khz 8 mhz frequency variation run mode due to temperature ? 0c to 105c ? -40c to 105c standby mode +/-1.5 +/- 1.5 unspecified +/-2 +/-3 % 32 khz output frequency 2 run mode ? -40c to 105c tbd 32 tbd khz 32 khz output frequency variation run mode due to temperature ? -40c to 105c +/-2.5 +/-4 % stabilization time ? 8 mhz output 3 ? 32 khz output 4 tstab 0.12 14.4 0.4 16.2 s output duty cycle 48 50 52 % 1. frequency after application of 8 mhz trim 2. frequency after application of 32 khz trim 3. standby to run mode transition 4. power down to run mode transition system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 37 general business information
figure 8. relaxation oscillator temperature variation (typical) after trim (preliminary) 8.4 memories and memory interfaces 8.4.1 flash memory characteristics table 22. flash timing parameters characteristic symbol min typ max unit longword program high-voltage time 1 thvpgm4 63 143 s sector erase high-voltage time 2 thversscr 13 113 ms erase block high-voltage time for 256 kb thversblk256k 52 452 ms 1. there is additional overhead that is part of the programming sequence. see the device reference manual for detail. 2. specifies page erase time. system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 38 preliminary freescale semiconductor, inc. general business information
8.4.1.1 flash timing specifications commands table 23. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk32k t rd1blk256k read 1s block execution time ? 32 kb data flash ? 256 kb program flash 0.5 1.7 ms ms t rd1sec1k read 1s section execution time (data flash sector) 60 s 1 t rd1sec2k read 1s section execution time (program flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersblk32k t ersblk256k erase flash block execution time ? 32 kb data flash ? 256 kb program flash 55 122 465 985 ms ms 2 t ersscr erase flash sector execution time 14 114 ms 2 t pgmsec512p t pgmsec512d t pgmsec1kp t pgmsec1kd program section execution time ? 512 b program flash ? 512 b data flash ? 1 kb program flash ? 1 kb data flash 2.4 4.7 4.7 9.3 ms ms ms ms t rd1all read 1s all blocks execution time 1.8 ms t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 175 1500 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t pgmpart32k program partition for eeprom execution time ? 32 kb flexnvm 70 ms t setramff t setram8k t setram32k set flexram function execution time: ? control code 0xff ? 8 kb eeprom backup ? 32 kb eeprom backup 50 0.3 0.7 0.5 1.0 s ms ms byte-write to flexram for eeprom operation t eewr8bers byte-write to erased flexram location execution time 175 260 s 3 table continues on the next page... system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 39 general business information
table 23. flash command timing specifications (continued) symbol description min. typ. max. unit notes t eewr8b8k t eewr8b16k t eewr8b32k byte-write to flexram execution time: ? 8 kb eeprom backup ? 16 kb eeprom backup ? 32 kb eeprom backup 340 385 475 1700 1800 2000 s s s word-write to flexram for eeprom operation t eewr16bers word-write to erased flexram location execution time 175 260 s t eewr16b8k t eewr16b16k t eewr16b32k word-write to flexram execution time: ? 8 kb eeprom backup ? 16 kb eeprom backup ? 32 kb eeprom backup 340 385 475 1700 1800 2000 s s s longword-write to flexram for eeprom operation t eewr32bers longword-write to erased flexram location execution time 360 540 s t eewr32b8k t eewr32b16k t eewr32b32k longword-write to flexram execution time: ? 8 kb eeprom backup ? 16 kb eeprom backup ? 32 kb eeprom backup 545 630 810 1950 2050 2250 s s s 1. assumes 25mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3. for byte-writes to an erased flexram location, the aligned word containing the byte must be erased. 8.4.1.2 reliability specifications table 24. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years table continues on the next page... system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 40 preliminary freescale semiconductor, inc. general business information
table 24. nvm reliability specifications (continued) symbol description min. typ. 1 max. unit notes n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree4k n nvmwree8k write endurance ? eeprom backup to flexram ratio = 16 ? eeprom backup to flexram ratio = 128 ? eeprom backup to flexram ratio = 512 ? eeprom backup to flexram ratio = 4096 ? eeprom backup to flexram ratio = 8192 35 k 315 k 1.27 m 10 m 20 m 175 k 1.6 m 6.4 m 50 m 100 m writes writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 3. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm (same value as data flash) and the allocated eeprom backup. minimum and typical values assume all byte-writes to flexram. 8.5 analog 8.5.1 12-bit cyclic analog-to-digital converter (adc) parameters table 25. 12-bit adc electrical specifications characteristic symbol min typ max unit recommended operating conditions supply voltage 1 v dda 2.7 3.3 3.6 v vrefh supply voltage 2 vrefhx 3.0 v dda v adc conversion clock 3 f adcclk 0.6 20 mhz conversion range r ad v refl v refh v input voltage range 4 external reference internal reference v adin v refl v ssa v refh v dda v timing and power conversion time t adc 6 adc clock cycles sample time t ads 1 5 adc clock cycles adc power-up time (from adc_pdn) t adpu 13 adc clock cycles table continues on the next page... system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 41 general business information
table 25. 12-bit adc electrical specifications (continued) characteristic symbol min typ max unit adc run current (per adc block) ? at 600 khz adc clock, lp mode ? 8.33 mhz adc clock, 00 mode ? 12.5 mhz adc clock, 01 mode ? 16.67 mhz adc clock, 10 mode ? 20 mhz adc clock, 11 mode i adrun 1 5 9 15 19 ma adc powerdown current (adc_pdn enabled) i adpwrdwn 0.02 a v refh current i vrefh 0.001 a accuracy (dc or absolute) integral non-linearity 5 i nl +/- 3 +/- 5 lsb 6 differential non-linearity 5 dnl +/- 0.6 +/- 1 lsb 6 monotonicity offset 7 ? 15 mhz adc clock internal/external reference ? >15 mhz adc clock internal/external reference v offset +/- 4.03 +/- 7.25 +/- 8.86 +/- 13.70 mv gain error e gain 0.801 to 0.809 0.798 to 0.814 mv ac specifications 8 signal to noise ratio snr 59 db total harmonic distortion thd 64 db spurious free dynamic range sfdr 65 db signal to noise plus distortion sinad 59 db effective number of bits enob 9.5 bits adc inputs input leakage current i in 0 +/-2 a input injection current 9 i inj +/-3 ma input capacitance sampling capacitor ? 1x mode ? 2x mode ? 4x mode c adi 1.4 2.8 5.6 pf 1. if the adcs reference is from v dda : when v dda is below 3.0 v, the adc functions but adc specifications are not guaranteed. 2. when the input is at the v refl level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset and gain error. when the input is at the v refh level the output will be all ones (hex fff), minus any error contribution due to offset and gain error. 3. adc clock duty cycle min/max is 45/55% 4. when v refh is supplied externally 5. i nl measured from v in = v refl to v in = v refh . 6. lsb = least significant bit = 0.806 mv at 3.3 v vdda, x1 gain setting system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 42 preliminary freescale semiconductor, inc. general business information
7. offset over the conversion range of 0025 to 4080 8. measured converting a 1 khz input full scale sine wave 9. the current that can be injected into or sourced from an unselected adc input without affecting the performance of the adc 8.5.1.1 equivalent circuit for adc inputs the following figure illustrates the adc input circuit during sample and hold. s1 and s2 are always opened/closed at non-overlapping phases and operate at the adc clock frequency. the following equation gives equivalent input impedance when the input is selected. freescale semiconductor 32 ? 1 (adc clockrate) x 1.4 x 10 -12 + 100 ohm + 125 ohm ? 1 2 3 analog input s1 s1 s2 c1 c1 s/h c1: single ended mode 2xc1: differential mode (v refhx - v reflx ) / 2 125 ? esd resisto r s2 s1 s1 channel mux equivalent resistance 100ohms c1: single ended mode 2xc1: differential mode 1. parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. 8 pf noise damping capacitor 4. sampling capacitor at the sample and hold circuit. capacitor c1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pf for x1 gain; 2.8pf for x2 gain, and 5.6pf for x4 gain 5. s1 and s2 switch phases are non-overlapping and operate at the adc clock frequency ? s 1 s 2 figure 9. equivalent circuit for a/d loading system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 43 general business information
8.5.2 16-bit sar adc electrical specifications 8.5.2.1 16-bit adc operating conditions table 26. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 2.7 3.6 v v dda supply voltage delta to v dd (v dd -v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss -v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high absolute v dda v dda v dda v 3 v refl adc reference voltage low absolute v ssa v ssa v ssa v 4 v adin input voltage v ssa v dda v c adin input capacitance ? 16 bit modes ? 8/10/12 bit modes 8 4 10 5 pf r adin input resistance 2 5 k r as analog source resistance 12 bit modes f adck < 4mhz 5 k 5 f adck adc conversion clock frequency 12 bit modes 1.0 18.0 mhz 6 f adck adc conversion clock frequency 16 bit modes 2.0 12.0 mhz 6 c rate adc conversion rate 12 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 7 c rate adc conversion rate 16 bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ksps 7 1. typical values assume v dda = 3.0 v, temp = 25c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. dc potential difference. 3. v refh is internally tied to v dda . 4. v refl is internally tied to v ssa . 5. this resistance is external to mcu. the analog source resistance should be kept as low as possible in order to achieve the best results. the results in this datasheet were derived from a system which has <8 analog source resistance. the r as / c as time constant should be kept to <1ns. 6. to use the maximum adc conversion clock frequency, the adhsc bit should be set and the adlpc bit should be clear. system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 44 preliminary freescale semiconductor, inc. general business information
7. for guidelines and examples of conversion rate calculation, download the adc calculator tool: http://cache.freescale.com/ files/soft_dev_tools/software/app_software/converters/adc_calculator_cnv.zip?fpsp=1 r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 10. adc input impedance equivalency diagram 8.5.2.2 16-bit adc electrical characteristics table 27. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 1.7 ma 3 f adack adc asynchronous clock source ? adlpc=1, adhsc=0 ? adlpc=1, adhsc=1 ? adlpc=0, adhsc=0 ? adlpc=0, adhsc=1 1.2 3.0 2.4 4.4 2.4 4.0 5.2 6.2 3.9 7.3 6.1 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12 bit modes ? <12 bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 16 bit modes ? 12 bit modes ? <12 bit modes -1 to +4 0.7 0.2 tbd -0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 16 bit modes ? 12 bit modes ? <12 bit modes 7.0 1.0 0.5 -2.7 to +1.9 -0.7 to +0.5 lsb 4 5 table continues on the next page... system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 45 general business information
table 27. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes e fs full-scale error ? 12 bit modes ? <12 bit modes -4 -1.4 -5.4 -1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16 bit modes ? 12 bit modes -1 to 0 0.5 lsb 4 enob effective number of bits 16 bit single-ended mode ? avg=32 ? avg=4 12 bit single-ended mode ? avg=32 ? avg=1 12.2 11.4 13.9 13.1 10.8 10.2 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16 bit single-ended mode ? avg=32 12 bit single-ended mode ? avg=32 -85 -74 db db 7 sfdr spurious free dynamic range 16 bit single-ended mode ? avg=32 12 bit single-ended mode ? avg=32 78 90 78 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the device's voltage and current operating ratings) temp sensor slope C40c to 105c 1.715 mv/c v temp25 temp sensor voltage 25c 722 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 46 preliminary freescale semiconductor, inc. general business information
3. the adc supply current depends on the adc conversion clock speed, conversion rate and the adlpc bit (low power). for lowest power operation the adlpc bit should be set, the hsc bit should be clear with 1mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock <16mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock <12mhz. 7. input data is 1 khz sine wave. adc conversion clock <12mhz. 8. system clock = 4 mhz, adc clock = 2 mhz, avg = max, long sampling = max figure 11. typical enob vs. adc_clk for 16-bit single-ended mode 8.5.3 12-bit digital-to-analog converter (dac) parameters table 28. dac parameters parameter conditions/comments symbol min typ max unit dc specifications resolution 12 12 12 bits settling time 1 at output load rld = 3 k? cld = 400 pf 1 s power-up time time from release of pwrdwn signal until dacout signal is valid t dapu 11 s accuracy table continues on the next page... system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 47 general business information
table 28. dac parameters (continued) parameter conditions/comments symbol min typ max unit integral non-linearity 2 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range inl +/- 3 +/- 4 lsb 3 differential non- linearity 2 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range dnl +/- 0.8 +/- 0.9 lsb 3 monotonicity > 6 sigma monotonicity, < 3.4 ppm non-monotonicity guaranteed offset error 2 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range v offset + 25 + 35 mv gain error 2 range of input digital words: 410 to 3891 ($19a - $f33) 5% to 95% of full range e gain +/- 0.5 +/- 1.5 % dac output output voltage range within 40 mv of either v ssa or v dda v out v ssa + 0.04 v v dda - 0.04 v v ac specifications signal-to-noise ratio snr 85 db spurious free dynamic range sfdr -72 db effective number of bits enob 11 bits 1. settling time is swing range from v ssa to v dda 2. no guaranteed specification within 5% of v dda or v ssa 3. lsb = 0.806mv 8.5.4 cmp and 6-bit dac electrical specifications table 29. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 2.7 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv table continues on the next page... system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 48 preliminary freescale semiconductor, inc. general business information
table 29. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 13 48 105 148 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 2 50 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 250 ns analog comparator initialization delay 3 40 s i dac6b 6-bit dac current adder (enabled) 7 a 6-bit dac reference inputs, vin1 and vin2 there are two reference input options selectable (via vrsel control bit). the reference options must fall within this range. v dda v dd v inl 6-bit dac integral non-linearity C0.5 0.5 lsb 4 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd -0.6v. 2. signal swing is 100 mv 3. comparator initialization delay is defined as the time between software writes to change control inputs (writes to dacen, vrsel, psel, msel, vosel) and the comparator output settling to a stable level. 4. 1 lsb = v reference /64 system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 49 general business information
0.04 0.05 0.06 0.07 0.08 p hystereris (v) 00 01 10 hystctr setting 0 0.01 0.02 0.03 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm 10 11 vin level (v) figure 12. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 0) system modules mc56f844xx advance information data sheet, rev. 2, 06/2012. 50 preliminary freescale semiconductor, inc. general business information
0 08 0.1 0.12 0.14 0.16 0.18 p hystereris (v) 00 01 10 hystctr setting 0 0.02 0.04 0.06 0.08 0.1 0.4 0.7 1 1.3 1.6 1.9 2.2 2.5 2.8 3.1 cm p 10 11 vin level (v) figure 13. typical hysteresis vs. vin level (v dd = 3.3 v, pmode = 1) pwms and timers 8.6.1 pwm characteristics table 30. pwm timing parameters characteristic symbol min typ max unit pwm clock frequency 60 100 mhz 8.6.2 quad timer timing parameters listed are guaranteed by design. 8.6 pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 51 general business information
table 31. timer timing characteristic symbol min 1 max unit see figure timer input period p in 2t + 6 ns figure 14 timer input high/low period p inhl 1t + 3 ns figure 14 timer output period p out 33 ns figure 14 timer output high/low period p outhl 16.7 ns figure 14 1. t = clock cycle. for 60 mhz operation, t = 16.7 ns. p out p outhl p outhl p in p inhl p inhl timer inputs timer outputs figure 14. timer timing 8.7 communication interfaces 8.7.1 queued serial peripheral interface (spi) timing parameters listed are guaranteed by design. table 32. spi timing characteristic symbol min max unit see figure cycle time master slave t c 55 55 ns ns figure 15 figure 16 figure 17 figure 18 enable lead time master slave t eld 17.5 ns ns figure 18 enable lag time master slave t elg 17.5 ns ns figure 18 table continues on the next page... pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. 52 preliminary freescale semiconductor, inc. general business information
table 32. spi timing (continued) characteristic symbol min max unit see figure clock (sck) high time master slave t ch 27.6 27.6 ns ns figure 15 figure 16 figure 17 figure 18 clock (sck) low time master slave t cl 27.6 27.6 ns ns figure 18 data set-up time required for inputs master slave t ds 27.6 1 ns ns figure 15 figure 16 figure 17 figure 18 data hold time required for inputs master slave t dh 1 3 ns ns figure 15 figure 16 figure 17 figure 18 access time (time to data active from high-impedance state) slave t a 5 ns figure 18 disable time (hold time to high- impedance state) slave t d 5 ns figure 18 data valid for outputs master slave (after enable edge) t dv 8.3 25 ns ns figure 15 figure 16 figure 17 figure 18 data invalid master slave t di 0 0 ns ns figure 15 figure 16 figure 17 figure 18 rise time master slave t r 1 1 ns ns figure 15 figure 16 figure 17 figure 18 fall time master slave t f 1 1 ns ns figure 15 figure 16 figure 17 figure 18 pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 53 general business information
sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14C1 lsb in t f t c=33.3 t cl t cl t r t r t f t ds t dh t ch t di t dv t di (ref) t r master msb out bits 14C1 master lsb out ss (input) t ch ss is held high on master t f figure 15. spi master timing (cpha = 0) sclk (cpol = 0) (output) sclk (cpol = 1) (output) miso (input) mosi (output) msb in bits 14C1 lsb in t r t c t cl t cl t f t ch t dv (ref) t dv t di (ref) t r t f master msb out bits 14C 1 master lsb out ss (input) t ch ss is held high on master t ds t dh t di t r t f figure 16. spi master timing (cpha = 1) pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. 54 preliminary freescale semiconductor, inc. general business information
sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14C1 t c t cl t cl t f t ch t di msb in bits 14C1 lsb in ss (input) t ch t dh t r t elg t eld t f slave lsb out t d t a t ds t dv t di t r figure 17. spi slave timing (cpha = 0) sclk (cpol = 0) (input) sclk (cpol = 1) (input) miso (output) mosi (input) slave msb out bits 14C1 t c t cl t cl t ch t di msb in bits 14C1 lsb in ss (input) t ch t dh t f t r slave lsb out t d t a t eld t dv t f t r t elg t dv t ds figure 18. spi slave timing (cpha = 1) pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 55 general business information
8.7.2 queued serial communication interface (sci) timing parameters listed are guaranteed by design. table 33. sci timing characteristic symbol min max unit see figure baud rate 1 br (f max /16) mbps rxd pulse width rxd pw 0.965/br 1.04/br ns figure 19 txd pulse width txd pw 0.965/br 1.04/br ns figure 20 lin slave mode deviation of slave node clock from nominal clock rate before synchronization f tol_unsynch -14 14 % deviation of slave node clock relative to the master node clock after synchronization f tol_synch -2 2 % minimum break character length t break 13 master node bit periods 11 slave node bit periods 1. f max is the frequency of operation of the sci clock in mhz, which can be selected system clock (max. 120 mhz depending on part number) or 2x system clock (max. 200 mhz) for the devices. rxd pw rxd sci receive data pin (input) figure 19. rxd pulse width txd pw txd sci transmit data pin (output) figure 20. txd pulse width 8.7.3 freescales scalable controller area network (flexcan) table 34. flexcan timing parameters characteristic symbol min max unit baud rate br can 1 mbps can wakeup dominant pulse filtered t wakeup 2 s can wakeup dominant pulse pass t wakeup 5 s pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. 56 preliminary freescale semiconductor, inc. general business information
? ? ? ? ? ? ? t wakeup can_rx can receive data pin (input) figure 21. bus wake-up detection 8.7.4 inter-integrated circuit interface (i 2 c) timing table 35. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.3 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 1 3.45 2 0 3 0.9 1 s data set-up time t su ; dat 250 4 100 2 , 5 ns rise time of sda and scl signals t r 1000 20 +0.1c b 6 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 5 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, a negative hold time can result, depending on the edge rates of the sda and scl lines. 2. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 3. input signal slew = 10ns and output load = 50pf 4. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 5. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 6. c b = total capacitance of the one bus line in pf. pwms and timers mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 57 general business information
? ? sda scl t hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r figure 22. timing definition for fast and standard mode devices on the i 2 c bus design considerations 9.1 thermal design considerations an estimation of the chip junction temperature, tj, can be obtained from the equation: t j = t a + (r ja x p d ) where, t a = ambient temperature for the package (c) r ja = junction-to-ambient thermal resistance (c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. unfortunately, there are two values in common usage: the value determined on a single-layer board and the value obtained on a board with two planes. for packages such as the pbga, these values can be different by a factor of two. which value is closer to the application depends on the power dissipated by other components on the board. the value obtained on a single layer board is appropriate for the tightly packed printed circuit board. the value obtained on the board with the internal planes is usually appropriate if the board has low-power dissipation and the components are well separated. when a heat sink is used, the thermal resistance is expressed as the sum of a junction-to- case thermal resistance and a case-to-ambient thermal resistance: r ja = r jc + r ca where, r ja = package junction-to-ambient thermal resistance (c/w) 9 design considerations mc56f844xx advance information data sheet, rev. 2, 06/2012. 58 preliminary freescale semiconductor, inc. general business information
r jc = package junction-to-case thermal resistance (c/w) r ca = package case-to-ambient thermal resistance (c/w) r jc is device related and cannot be adjusted. you control the thermal environment to change the case to ambient thermal resistance, r ca . for instance, you can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. to determine the junction temperature of the device in the application when heat sinks are not used, the thermal characterization parameter (yjt) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: t j = t t + ( jt x p d ) where, t t = thermocouple temperature on top of package (c/w) jt = hermal characterization parameter (c/w) p d = power dissipation in package (w) the thermal characterization parameter is measured per jesd51C2 specification using a 40-gauge type t thermocouple epoxied to the top center of the package case. the thermocouple should be positioned so that the thermocouple junction rests on the package. a small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. the thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. when heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. a clearance slot or hole is normally required in the heat sink. minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. from this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. design considerations mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 59 general business information
9.2 electrical design considerations caution this device contains protective circuitry to guard against damage due to high static voltage or electrical fields. however, take normal precautions to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. use the following list of considerations to assure correct operation of the device: ? provide a low-impedance path from the board power supply to each v dd pin on the device and from the board ground to each v ss (gnd) pin. ? the minimum bypass requirement is to place 0.01C0.1f capacitors positioned as near as possible to the package supply pins. the recommended bypass configuration is to place one bypass capacitor on each of the v dd /v ss pairs, including v dda /v ssa . ceramic and tantalum capacitors tend to provide better tolerances. ? ensure that capacitor leads and associated printed circuit traces that connect to the chip v dd and v ss (gnd) pins are as short as possible. ? bypass the v dd and v ss with approximately 100 f, plus the number of 0.1 f ceramic capacitors. ? pcb trace lengths should be minimal for high-frequency signals. ? consider all device loads as well as parasitic capacitance due to pcb traces when calculating capacitance. this is especially critical in systems with higher capacitive loads that could create higher transient currents in the v dd and v ss circuits. ? take special care to minimize noise levels on the v ref , v dda , and v ssa pins. ? using separate power planes for v dd and v dda and separate ground planes for v ss and vssa are recommended. connect the separate analog and digital power and ground planes as near as possible to power supply outputs. if an analog circuit and digital circuit are powered by the same power supply, you should connect a small inductor or ferrite bead in serial with v dda and v ssa traces. ? physically separate analog components from noisy digital components by ground planes. do not place an analog trace in parallel with digital traces. place an analog ground trace around an analog signal trace to isolate it from digital traces. ? because the flash memory is programmed through the jtag/eonce port, spi, sci, or i 2 c, the designer should provide an interface to this port if in-circuit flash programming is desired. ? if desired, connect an external rc circuit to the reset pin. the resistor value should be in the range of 4.7 k ?C 10 k ? ; the capacitor value should be in the range of 0.22 fC4.7 f. design considerations mc56f844xx advance information data sheet, rev. 2, 06/2012. 60 preliminary freescale semiconductor, inc. general business information
? configuring the reset pin to gpio output in normal operation in a high-noise environment may help to improve the performance of noise transient immunity. ? add a 2.2 k ? external pullup on the tms pin of the jtag port to keep eonce in a restate during normal operation if jtag converter is not present. ? during reset and after reset but before i/o initialization, all i/o pins are at tri-state. ? to eliminate pcb trace impedance effect, each adc input should have a no less than 33 pf 10 ? rc filter. 10 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to http://www.freescale.com and perform a keyword search for the drawings document number: drawing for package document number to be used 48-pin lqfp 98ash00962a 64-pin lqfp 98ass23234w 11 pinout 11.1 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the sim's gps registers are responsible for selecting which alt functionality is available on most pins. 64 lqfp 48 lqfp pin name default alt0 alt1 alt2 alt3 1 1 gpiod2 2 2 resetb resetb gpiod4 3 3 gpioc0 gpioc0 extal clkin0 4 4 gpioc1 gpioc1 xtal 5 5 gpioc2 gpioc2 txd0 tb0 xb_in2 clko0 6 gpiof8 gpiof8 rxd0 tb1 cmpd_o 7 6 gpioc3 gpioc3 ta0 cmpa_o rxd0 clkin1 8 7 gpioc4 gpioc4 ta1 cmpb_o xb_in8 ewm_out_b 9 gpioa7 gpioa7 ana7&anc11 10 gpioa6 gpioa6 ana6&anc10 obtaining package dimensions mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 61 general business information
64 lqfp 48 lqfp pin name default alt0 alt1 alt2 alt3 11 gpioa5 gpioa5 ana5&anc9 12 8 gpioa4 gpioa4 ana4&anc8&cmpd_in0 13 9 gpioa0 gpioa0 ana0&cmpa_in3 cmpc_o 14 10 gpioa1 gpioa1 ana1&cmpa_in0 15 11 gpioa2 gpioa2 ana2&vrefha&cmpa_in1 16 12 gpioa3 gpioa3 ana3&vrefla&cmpa_in2 17 gpiob7 gpiob7 anb7&anc15&cmpb_in2 18 13 gpioc5 gpioc5 daco xb_in7 19 gpiob6 gpiob6 anb6&anc14&cmpb_in1 20 gpiob5 gpiob5 anb5&anc13&cmpc_in2 21 14 gpiob4 gpiob4 anb4&anc12&cmpc_in1 22 15 vdda vdda 23 16 vssa vssa 24 17 gpiob0 gpiob0 anb0&cmpb_in3 25 18 gpiob1 gpiob1 anb1&cmpb_in0 26 19 vcap vcap 27 20 gpiob2 gpiob2 anb2&vrefhb&cmpc_in3 28 21 gpiob3 gpiob3 anb3&vreflb&cmpc_in0 29 vdd vdd 30 22 vss vss 31 23 gpioc6 gpioc6 ta2 xb_in3 cmp_ref 32 24 gpioc7 gpioc7 ss0_b txd0 33 25 gpioc8 gpioc8 miso0 rxd0 xb_in9 34 26 gpioc9 gpioc9 sck0 xb_in4 35 27 gpioc10 gpioc10 mosi0 xb_in5 miso0 36 28 gpiof0 gpiof0 xb_in6 tb2 sck1 37 29 gpioc11 gpioc11 cantx scl1 txd1 38 30 gpioc12 gpioc12 canrx sda1 rxd1 39 gpiof2 gpiof2 scl1 xb_out6 40 gpiof3 gpiof3 sda1 xb_out7 41 gpiof4 gpiof4 txd1 xb_out8 42 gpiof5 gpiof5 rxd1 xb_out9 43 31 vss vss 44 32 vdd vdd 45 33 gpioe0 gpioe0 pwma_0b 46 34 gpioe1 gpioe1 pwma_0a 47 35 gpioe2 gpioe2 pwma_1b 48 36 gpioe3 gpioe3 pwma_1a 49 37 gpioc13 gpioc13 ta3 xb_in6 ewm_out_b 50 38 gpiof1 gpiof1 clko1 xb_in7 cmpd_o 51 39 gpioe4 gpioe4 pwma_2b xb_in2 pinout mc56f844xx advance information data sheet, rev. 2, 06/2012. 62 preliminary freescale semiconductor, inc. general business information
64 lqfp 48 lqfp pin name default alt0 alt1 alt2 alt3 52 40 gpioe5 gpioe5 pwma_2a xb_in3 53 gpioe6 gpioe6 pwma_3b xb_in4 pwmb_2b 54 gpioe7 gpioe7 pwma_3a xb_in5 pwmb_2a 55 41 gpioc14 gpioc14 sda0 xb_out4 56 42 gpioc15 gpioc15 scl0 xb_out5 57 43 vcap vcap 58 gpiof6 gpiof6 tb2 pwma_3x pwmb_3x xb_in2 59 gpiof7 gpiof7 tb3 cmpc_o ss1_b xb_in3 60 44 vdd vdd 61 45 vss vss 62 46 gpiod1 63 47 gpiod3 64 48 gpiod0 11.2 pinout diagrams the following diagrams show pinouts for the packages. for each pin, the diagrams show the default function. however, many signals may be multiplexed onto a single pin. pinout mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 63 general business information
gpiob5 gpiob6 gpioc5 gpiob7 gpioa3 gpioa2 gpioa1 gpioa0 gpioa4 gpioa5 gpioa6 gpioa7 gpioc4 gpioc3 gpiof8 gpioc2 gpioc1 gpioc0 resetb 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 vss vdd gpiof7 gpiof6 vcap gpioc15 gpioc14 gpioe7 gpioe6 gpioe5 gpioe4 gpiof1 gpioc13 gpioe3 gpioe2 gpioe1 gpioe0 vdd vss gpiof5 gpiof4 gpiof3 gpiof2 gpioc12 gpioc11 gpiof0 gpioc10 gpioc9 gpioc8 gpioc7 gpioc6 vss vdd gpiob3 gpiob2 vcap gpiob1 gpiob0 vssa vdda gpiob4 figure 23. 64-pin lqfp pinout mc56f844xx advance information data sheet, rev. 2, 06/2012. 64 preliminary freescale semiconductor, inc. general business information
gpioa3 gpioa2 gpioa1 gpioa0 gpioa4 gpioc4 gpioc3 gpioc2 gpioc1 gpioc0 resetb 12 11 10 9 8 7 6 5 4 3 2 1 48 47 46 45 44 43 42 41 40 39 38 37 vss vdd vcap gpioc15 gpioc14 gpioe5 gpioe4 gpiof1 gpioc13 36 35 34 33 gpioe3 gpioe2 gpioe1 gpioe0 32 31 30 29 28 27 26 25 vdd vss gpioc12 gpioc11 gpiof0 gpioc10 gpioc9 gpioc8 gpiob2 vcap gpiob1 gpiob0 24 23 22 21 20 19 18 17 vssa vdda gpiob4 gpioc5 16 15 14 13 gpioc7 gpioc6 vss gpiob3 figure 24. 48-pin lqfp 12 product documentation the documents listed in table 36 are required for a complete description and proper design with the device. documentation is available from local freescale distributors, freescale semiconductor sales offices, or online at http://www.freescale.com . product documentation mc56f844xx advance information data sheet, rev. 2, 06/2012. freescale semiconductor, inc. preliminary 65 general business information
table 36. device documentation topic description document number dsp56800e/dsp56800ex reference manual detailed description of the 56800ex family architecture, 32-bit digital signal controller core processor, and the instruction set dsp56800erm mc56f844xx reference manual detailed functional description and programming model mc56f844xxrm serial bootloader user guide detailed description of the serial bootloader in the dsc family of devices tbd mc56f844xx data sheet electrical and timing specifications, pin descriptions, and package information (this document) mc56f844xx mc56f84xxx errata details any chip issues that might be present mc56f84xxx_0n27e 13 revision history the following table summarizes changes to this document since the release of the previous version. table 37. revision history rev. date substantial changes 2 06/2012 this is the first publicly released version of this document. revision history mc56f844xx advance information data sheet, rev. 2, 06/2012. 66 preliminary freescale semiconductor, inc. general business information
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com document number: mc56f844xx rev. 2, 06/2012 preliminary general business information information in this document is provided solely to enable system and software implementers to use freescale semiconductors products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any liability, including without limitation consequential or incidental damages. "typical" parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals", must be validated for each customer application by customer's technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claims alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as their non-rohs-complaint and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale's environmental products program, go to http://www.freescale.com/epp. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? 2012 freescale semiconductor, inc.

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